1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to a power reduction circuit in a semiconductor integrated circuit.
2. Background of the Related Art
In a semiconductor integrated circuit, unnecessary power consumption can be reduced by controlling the value of a supply voltage according to a power consumption adjustment from an external source or a control signal thereof. For example, when the control signal of the power consumption adjustment is not externally supplied during a predetermined time period, the power reduction circuit converts the semiconductor integrated circuit to a standby mode and reduces the supply voltage. In the standby mode, upon detecting the control signal for the power consumption adjustment, the power reduction circuit again applies the supply voltage at the original level to operate the semiconductor integrated circuit normally.
A related art power reduction circuit is shown in FIG. 1. As shown in FIG. 1, resistors R1 and R2 are connected to the terminals of power supplies VDD and VSS, respectively. Local power supplies VDD.sub.-- L and VSS.sub.-- L are generated through the resistors R1 and R2, respectively.
Switching devices Q1 and Q4 are connected in parallel to the resistors R1 and R2, respectively. The PMOS transistor Q1 is controlled by the inverted active signal/ACT. When the inverted active signal/ACT is at a low level, Q1 is turned on and short-circuits the VDD terminal and VDD.sub.-- L terminal. The NMOS transistor Q4 is controlled by the active signal ACT. When the active signal ACT is at a high level, Q4 is turned on and short-circuits the VSS terminal and VSS.sub.-- L terminal.
A CMOS inverter is inserted between terminals of VDD.sub.-- L and VSS.sub.-- L, which is composed of the PMOS transistor Q2 and the NMOS transistor Q3. Each of the transistors Q2 and Q3 has a lower threshold voltage Vt than any other MOS transistor for realizing a high-speed operation.
FIG. 2. shows a power reduction circuit having MOS transistors instead of the voltage reduction device of FIG. 1. As a voltage reduction device, the NMOS transistor Q5 and PMOS transistor Q6 are connected to the terminals of VDD and VSS, respectively. Each transistor Q5 and Q6 operates as a resistor device by the short-circuit of its gate and source.
The power supply voltage VDD and the local power supply voltage VDD.sub.-- L have a voltage difference as much as the threshold voltage Vtn of the NMOS transistor Q5.
In other words, VDD.sub.-- L=VDD-Vtn is applied. The ground voltage VSS and the local ground voltage VSS.sub.-- L have also a voltage difference as much as the threshold voltage Vtp of the PMOS transistor Q6. That is, VSS.sub.-- L=VSS+Vtp is applied.
In the active mode, when the active signal ACT is at a high level and the inverted active signal/ACT is at a low level, The transistor Q1 is turned on. At this time, VDD.sub.-- L=VDD is applied, if a voltage drop due to Vtp of the transistor Q1 is not considered. The transistor Q4 is also turned on and VSS.sub.-- L=VSS is applied if a voltage drop due to Vtn of the transistor Q4 is not considered. Therefore, when ACT is brought to a high level, the transistors Q5 and Q6 do not affect VDD.sub.-- L and VSS.sub.-- L. In this state, the CMOS inverter generates the output signal OUT of the level of VDD or VSS according to the logic value of the input signal IN.
In the standby mode, the signal ACT becomes a low level and/ACT a high level. These signals respectively turn off the transistors Q1 and Q4. The current path between terminals of VDD and VDD.sub.-- L is made by The transistor Q5 and the current path between terminals of VSS and VSS.sub.-- L by the transistor Q6. In the standby mode, the CMOS inverter generates the output signal OUT of the level of VDD.sub.-- L or VSS.sub.-- L according to the logic value of the input signal IN.
In the related art power reduction circuit, the threshold voltages Vtn and Vtp of the transistors Q5 and Q6 are determined based on an expected power reduction. If the power reduction is expected to be high, Vtn and Vtp of the transistors Q5 and Q6 should be raised to lower VDD.sub.-- L. However, if Vtn and Vtp are large, the switching from the standby mode to the active mode takes longer.
As described above, the related art power reduction circuit has various disadvantages. If Vtn and Vtp are not small enough to be realized a resistor device, good power reduction will not result. If Vtn and Vtp are set large considering only the power reduction, the switching time from the standby mode to the active mode becomes too long, and it is difficult to perform a high-speed operation. Thus, the threshold voltage Vtn or Vtp can only be set to comply with one of a good power reduction and a good operation speed.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.